UHF frequency synthesizer mm range. Microwave laboratory synthesizer. Scheme, description. Satellite and cellular communications, wireless data infrastructures: requirements for components

The creation of modern communication facilities is impossible without the use of high-quality frequency synthesizers, which largely determine the technical parameters of the radio system. The article discusses high-performance broadband frequency synthesizers, and production of the company Maxim integrated, which allow you to generate a reference signal in the range of 0.25 ... 10 GHz. Their low cost and excellent phase noise performance makes them suitable for a wide range of applications, from personal radio systems to high-quality instrumentation.

Humanity is more and more actively using the radio-frequency part of the spectrum of electromagnetic waves, in particular - the range of ultra-short waves with a frequency of 0.30 ... 30 GHz. Today, this vast range is already quite densely filled with various radio communication systems with channels for transmitting digital data, and is entangled in a network infrastructure of a local and global scale. The emergence of new systems and standards for wireless communications, satellite communications and navigation systems is paralleling advances in semiconductor manufacturing technologies and is driving rapid advances in communications capabilities.

Satellite and cellular communications, wireless data infrastructures: requirements for components

One of the fundamental design challenges for any RF equipment is to ensure high accuracy and stability of the carrier frequency, including amplitude and phase. This problem is solved today, as a rule, with the use of specialized frequency synthesizers. A common variant in this case is a synthesizer chip with a phase-locked loop (PLL), which uses an external crystal oscillator of the reference frequency together with built-in dividers for the reference and generated output frequency, a comparison circuit in the form of a frequency-phase discriminator (detector). The discrepancy signal is generated by a separate output stage (Charge Pump) and fed through an external (loop) filter to a voltage controlled oscillator (VCO), which can be either built-in or external.

Programmable coefficients for Integer-N and Fractional-N modes, as well as the selection of the appropriate reference frequency, provide an extended range of output frequencies and allow you to vary such parameters of the frequency synthesis process as the speed and step of frequency switching, the level of phase noise.

Fractional-N synthesizers appeared largely as a solution to the problem of increasing the frequency switching speed, reducing phase noise near the carrier frequency and reducing the level of spurious components in GSM and GPRS communication systems.

Synthesizers MAX2870, MAX2871, MAX2880. Features, benefits, recommendations for use

In the model range of semiconductor components of the Maxim Integrated company today there are three microcircuits of ultra-wideband frequency synthesizers with phase-locked loop (PLL). They all use a synthesis mechanism based on self-oscillating PLLs. The output frequency is controlled by the VCO and stabilized by a low frequency reference oscillator.

Table 1. Maxim Itegrated frequency synthesizers with PLL

Name	Mode synthesis	Supply voltage, V	Frequency range, MHz		Out. power, dBm	Diff. exits	Noise level, dBc / Hz	Instability cf. square	Case / Leads	Working temperature, ° C
			Min.	Max.
MAX2870	Fractional / Integer	3,0…3,6	23,5	6000	-4…5	2	-226,4	0,25	TQFN / 32	-40…85
MAX2871	Fractional / Integer	3,0…3,6	23,5	6000	-4…5	2	-229	0,2	TQFN / 32	-40…85
MAX2880	Fractional / Integer	2,8…3,6	250	12400	No	No	-229	0,14	TQFN / 20 TSSOP / 16	-40…85

Applications for Maxim Integrated frequency synthesizers include telecommunications equipment, wireless communication equipment, measurement systems, clock generators in RF devices and analog-to-digital converters.

Synthesizer MAX2870

The ultra-wideband, phase-locked MAX2870 with integrated VCO is capable of both integer and fractional synthesis modes. Combined with an external reference generator and external filter MAX2870 allows to create highly efficient, low-noise circuits in the range of 23.5 MHz ... 6 GHz.

Frequency generation in the extended range is provided by several integrated VCOs and output dividers with ratios of 1 ... 28. There are two software-settable independent differential outputs that can provide an output power of -4 ... 5 dBm. Both outputs can be disabled by software or hardware.

The MAX2870 is controlled via a 3-wire serial interface. The microcircuit is available in a miniature, 32-pin QFN package. It is capable of operating in the temperature range -40 ... 85 ° C.

A functional diagram of the MAX2870 is shown in Figure 1. The main elements of the device are the SPI AND REGISTERS block, several counters and dividers, several VCOs and multiplexers. Four output signals (RFOUTx_x) are taken through switches from two differential amplifiers. There is a CHARGE PUMP block and a TUNE input for tuning the synthesized frequency.

To control the MAX 2870, there are five 32-bit registers for writing data, and one register for reading. The most significant 29 bits (MSB) are for data, and the most significant 3 bits (LSB) define the register address. Data in registers is loaded via the serial SPI interface, 29 bits of MSB are transmitted first. The programmable registers have addresses 0x05, 0x04, 0x03, 0x02, 0x01 and 0x00.

Figure 2 is a timing diagram of the SPI write process. After power-up, all registers must be programmed twice with a minimum pause of 20 ms between writes. The first entry allows you to make sure that the device is turned on, and the second one starts the VCO.

The MAX2870 can go into hibernation mode by setting SHDN = 1 (register 2, bit 5) or by setting the CE pin low. After exiting the hibernation mode, it takes at least 20 ms for the external capacitors to charge before programming the VCO frequency.

The input reference frequency goes through the RF_IN input to the inverting buffer and then through the optional x2 multiplier and multiplexer to the R COUNTER divider, then through the optional divider and multiplexer it reaches the phase detector and the output multiplexer.

When the x2 multiplier is enabled (DBR = 1), the maximum reference frequency is limited to 100 MHz. When the multiplier is disabled, the reference input frequency is limited to 200 MHz. The minimum reference frequency is 10 MHz. The minimum division ratio R is 1 and the maximum is 1023.

The phase detector frequency is determined as follows:

where fREF is the frequency of the input reference signal. DBR (register 2, bit 25) sets the input frequency doubling mode fREF. RDIV2 (register 2, bit 24) sets the division mode of fREF to 2. R (register 2, bits 23:14) represents the value of a 10-bit programmable counter (1 to 1023). The maximum fPFD value is 50 MHz for Frac-N mode and 105 MHz for Int-N mode. The R divisor can be cleared when RST (register 2, bit 3) is 1.

The VCO frequency (fVCO), N, F and M values ​​can be determined based on the desired channel A output frequency (fRFOUTA) as follows. The divisor DIVA can be set based on the fRFOUTA values ​​from the DIVA value table (register 4, bits 22 ... 20).

If FB = 1, (DIVA is excluded from PLL feedback):

If FB = 0, (DIVA in PLL feedback) and DIVA ≤ 16:

If FB = 0, (DIVA in PLL feedback) and DIVA> 16:

Here N is the value of the 16-bit counter N (16 ... 65535) programmed through register 0, bits 30 ... 15. M - fractional modulus value (2 ... 4095), programmed through bits 14 ... 3 of register 1. F - fractional division value, programmed through bits 14 ... 3 of register 0.

In fractional (Frac-N) mode, the minimum N is 19 and the maximum is 4091. The N counter is reset when RST is 1 (register 2, bit 3). DIVA - setting the division of the RF output (0 ... 7), programmed through bits 22 ... 20 of register 4. The division factor is set as 2DIVA.

The output frequency of channel B (fRFOUTB) is determined as follows:

If BDIV = 0 (register 4, bit 9),

If BDIV = 1,

Int-N / Frac-N Modes

Integer division mode (Int-N) is selected by setting bit INT = 1 (register 0, bit 31). When operating in this mode, the LDF bit (register 2, bit 8) must also be set to enable the function of determining the timing (frequency lock) in Integer-N mode.

Fractional division mode (Frac-N) is selected by setting bit INT = 0 (register 0, bit 31). Additionally, set LDF bit = 0 (register 2, bit 8) for Frac-N timing mode.

If the device stays in Frac-N mode with a fractional division of F = 0, unwanted impulse noise may occur. To avoid this, auto-switch to Integer-N mode can be enabled when F = 0 by setting bit F01 = 1 (register 5, bit 24).

Phase detector and control voltage generation (Charge Pump)

The charge current generated by Charge Pump for the external capacitor is determined by the value of the resistor connected between the RSET pin and the common wire, and the value of the CP bit (register 2, bits 12 ... 9) as follows:

To improve stability in Frac-N mode, set CPL linearity bit = 1 (register 1, bits 30, 29). For Int-N mode, set CPL = 0. To reduce noise in Int-N mode, set CPOC bit = 1 (register 1, bit 31) to prevent current leakage into the loop filter. For Frac-N mode, set CPOC = 0.

The CP_OUT output can be set to a high impedance state when TRI = 1 (register 2, bit 4). When TRI = 0, this output is in normal state. The polarity of the phase detector signal can be reversed for an active inverting loop filter. For a non-inverting filter, set PDP = 1 (register 2, bit 6). For inverting filter set PDP = 0.

MUX_OUT and LD (Lock Detect) outputs

MUX_OUT is a multipurpose test output for monitoring various internal MAX2870 operations. MUX_OUT can also be configured for serial data output. The MUX bits (register 2, bits 28 ... 26) allow you to select the type of signal on MUX_OUT.

The Lock detect signal can be monitored via the LD output by setting the LD bits (register 5, bits 23 ... 22). For digital timing detection, set LD = 01. Digital timing detection depends on the synthesis mode. In Frac-N mode, set LDF = 0, and in Int-N mode, set LDF = 1. You can also set the digital timing accuracy according to the tables.

Analog timing detection can be used with LD = 10. In this mode, LD uses an open collector output that requires an external pull-up resistor.

The accuracy of the timing determination output depends on many factors. The output may be invalid during the VCO autoselection process. At the end of this process, the output is still unreliable until the tuning voltage is established. VTUNE settling time depends on the loop filter bandwidth and can be calculated using the EE-Simulation software tool.

Fast-Lock Mode

The MAX2870 has a Fast-Lock mode. In this mode CP = 0000 (register 2, bits 12 ... 9), and a divider of two resistors with a ratio of 1/3 nominal values ​​is connected to the SW output. A larger resistor is connected between the output and the common power terminal, and a smaller resistor is connected between the SW terminal and the filter capacitor. When CDM = 01 (register 3, bits 16 ... 15), fast sync starts after the VCO autoselect (VAS) process is complete.

During accelerated synchronization, the charging current of the Charge Pump increases to the value determined by CP = 1111, and the ratio between the resistors shunting the loop filter becomes 1/4 due to the high impedance state of the SW output. Fast-Lock is deactivated at the end of a user-definable timeout. This timeout is:

Here M is the adjustable factor and CDIV is the divisor setting. The designer should determine the CDIV settings based on the feedback filter time constant.

RFOUTA ± and RFOUTB ± outputs

The IC has two open collector differential RF outputs that require external 50 ohm resistors to be connected to each of the outputs.

Each output can be independently enabled and disabled by setting bits RFA_EN (register 4, bit 5) and RFB_EN (register 4, bit 8). Both outputs can also be monitored via the RFOUT_EN pin.

The power output of each output is individually configurable via APWR (register 4, bits 4, 3) for RFOUTA and BPWR (register 4, bits 7 ... 6) for RFOUTB. It is possible to adjust the power of the differential output in the range of -4 ... 5 dBm, with a step of 3 dB when operating at a load of 50 Ohm. Adjustment is also possible in the same range for the single-ended output with supply through an RF choke. Different loading elements are required for optimal output level over the entire frequency range. If an unbalanced output is used, the unused output must be connected to an appropriate load (Table 2).

Table 2. Purpose of MAX2870 terminals

Output	Name	Function
1	CLK	Synchronization line (input)
2	DATA	Serial data (input)
3	LE
4	CE	Chip Select - Low
5	SW	Fast switching. Connects the feedback filter in PLL mode
6	VCC_CP
7	CP_OUT	Charge pump output
8	GND_CP	General conclusion for the charge pump generator
9	GND_PLL	General PLL output
10	VCC_PLL	PLL power supply
11	GND_RF	General output of RF circuits. Connects to the ground bus of the main board
12	RFOUTA_P	Open collector positive RF output A. Connects to power supply via RF choke or 50 ohm load
13	RFOUTA_N	Open collector negative RF output A. Connects to power supply via RF choke or 50 ohm load
14	RFOUTB_P	Open collector positive RF output B. Connects to power supply via RF choke or 50 ohm load
15	RFOUTB_N	Open collector negative RF output B. Connects to power supply via RF choke or 50 ohm load
16	VCC_RF
17	VCC_VCO	VCO power supply
18	GND_VCO	General conclusion of the VCO. Connects to the common bus of the main board
19	NOISE_FILT	Noise decoupling pin of the VCO. Connects through 1 μF to the ground bus of the main board
20	TUNE	VCO control input. Connects to an external filter
21	GND_TUNE	Common output of the VCO control input. Connects to the ground bus of the main board
22	RSET	Charge pump input current range setting input
23	BIAS_FILT	Noise decoupling of the VCO. Connected through 1 μF to the common pin
24	REG	Reference voltage correction. Connected through 1 μF to the common pin
25	LD	Synchronization mode output. High level in synchronization mode, low level - if there is no synchronization.
26	RFOUT_EN	Turns on the RF output. RF outputs are disabled when low
27	GND_DIG	Common pin for digital circuits. Connects to the ground bus of the main board
28	VCC_DIG	Power supply for digital circuits
29	REF_IN	Frequency reference input
30	MUX_OUT	Multiplexer output and serial data output
31	GND_SD
32	VCC_SD
–	EP	Heat sink area. Connects to the common power bus of the main board

VCO

The microcircuit contains four separate 16-band VCO units, which provide continuous coverage of the 3 ... 6 GHz frequency range. For the VCO to work, the output of the external feedback filter must be connected to the TUNE input, which controls the VCO operation. The control voltage comes through the filter from the CP_OUT output (Figure 3).

The MAX2870 contains a 3-bit ADC for reading the VCO voltage setting range. ADC values ​​can be read from register 6, bits 22 ... 20.

Remember that a lock detect signal may appear if the VCO tuning voltage is outside the appropriate range.

Auto VCO

The VCO autoselect mode (VAS) is enabled when the VAS_SHDN = 0 bit (register 3, bit 25) is set. If VAS_SHDN = 1, then the VCO can be manually set via the VCO bits (register 3, bits 31 ... 26). The RETUNE bit (register 3, bit 24) is used to enable / disable the VCO autoselect function. If RETUNE = 1 and the ADC detects that the VTUNE tuning voltage is between 000 and 111, the VAS function initiates auto tuning. If RETUNE = 0, this function is disabled.

The sync frequency fBS should be 50 kHz. It is set by the BS bits (register 4, 19 ... 12). The required BS value is calculated by the formula:

Where fPFD is the phase detector frequency. The BS value should be rounded to the nearest whole number. If the calculated BS value is above 1023, then BS = 1023. If fPFD is below 50 kHz, then BS = 1. The time required to correctly select the VCO is 10 / fBS.

Phase adjustment

Once the set frequency has been established, the phase of the RF output can be discretely changed in P / M × 360 ° steps. The phase cannot be determined absolutely, but it can be changed relative to the current value.

To change the phase, do the following:

• set the set frequency at the output;
• set the phase increment relative to the current value P = M × (phase change) / 360 °;
• enable phase change by setting CDM = 10;
• reset CDM by setting it to 0.

Synthesizer MAX2871

Ultra wideband MAX2871 with PLL and integrated VCO, it can operate in both integer and fractional frequency synthesis modes. Combined with an external reference generator and loop filter, the MAX2871 finds use in high performance, low noise applications operating in the 0.235 ... 6 GHz range. The MAX2871 also includes four integrated VCOs and two differential outputs with software power level control of -4 ... 5 dBm. Both outputs can be disabled by software or hardware.

The microcircuit is available in a miniature 32-pin QFN package. It is completely interchangeable with the MAX2870. The MAX2871 operates over a -40 ... 85 ° C temperature range. The functional block diagram of the MAX2871 is the same as that of the MAX2870 (Figure 1). However, the MAX2871 has advanced functionality that differs reduced level noise and includes a built-in temperature sensor with a 7-bit ADC with an accuracy of ± 3 ° C.

VCO voltage setting

Unlike the 3-bit ADC in the MAX2870, the MAX2871 uses a 7-bit ADC to read the VCO voltage and can be read through register 6, bits 22 ... 16. To digitize the voltage, you need to do the following:

• set bits CDIV (register 3, bits 14 ... 3) = fPFD / 100 kHz to select the clock frequency for the ADC;
• set the ADCM bits (register 5, bits 5 ... 3) = 100 to enable the ADC to read the voltage at the TUNE pin;
• set ADCS (register 5, bit 6) = 1 to start the ADC conversion process;
• wait 100 μs until the process is complete;
• read the value of register 6. The ADC value is located in bits 22 ... 16;
• clear bits ADCM = 0 and ADCS = 0.

The voltage at the TUNE pin can be calculated as follows:

Auto VCO

Additional options are available for the MAX2871 during the selection of the VCO to use. The VAS_TEMP bit (register 3, bit 24) can be used to select the optimal VCO according to the ambient temperature to ensure synchronization stability in the -40 ... 85 ° C range. During VCO selection, bits RFA_EN (register 4, bit 5) and RFB_EN (register 4, bit 8) must be set to 0, and bits 30, 29 of register 5 must be set to 11. Setting VAS_TEMP = 1 will increase the time required to set the reference frequency by approximately 10 / fBS to 100 ms.

temperature sensor

To calculate the temperature of the crystal, the MAX2871 has a built-in temperature sensor with a 7-bit ADC, the state of which is read through register 6. In this case, you need to do almost the same sequence of steps as when adjusting the VCO voltage. The exception is the second point:

• set the ADCM bits (register 5, bits 5 ... 3) = 001 to enable the ADC to read the temperature.

An approximate temperature can be obtained as follows:

This formula is most accurate when the VCO is enabled and at full power output at RFOUTA.

RFOUTA ± and RFOUTB ± outputs

Where CDIV (register 3, bits 14 ... 3) is the 12-bit divider value, M (register 1, bits 14 ... 3) is the variable factor for the fractional converter N, and fPFD is the phase detector frequency.

PLL Tracking Disruption

To ensure stability of the set frequency synchronization, in addition to the Fast-Lock method, the MAX2871 has Cycle Slip reduction, which is allowed by setting the CSM bit (register 3, bit 18) to 1. This mode provides the minimum value of the control charge pumping current at the CP block output.

Compared to the MAX2870, the MAX2871 also has enhanced capabilities for adjusting the phase of the output frequency signal.

Synthesizer MAX2880

The final model in the Maxim Integrated line of synthesizers is MAX2880 with a PLL system that uses an external VCO and is capable of operating in an even wider frequency range. Together with an external reference oscillator, VCO and filter, the MAX2880 generates low noise RF frequencies at the output in the range of 0.25 ... 12.4 GHz. The MAX2880 uses a built-in temperature sensor. It is available in two versions: a 20-lead TQFN package and a 16-lead TSSOP package, which are capable of operating in an extended operating temperature range of -40 ... 85 ° C.

A block diagram of the MAX2880 is shown in Figure 4. The principle of operation and a number of components are similar to those used in the MAX2870 and MAX2871. The MAX2880 includes a high precision low noise phase detector (PFD) and a precision loop filter capacitor Charge Pump, a 10-bit programmable reference divider, a 16-bit Integer N divider, and a 12-bit variable ratio fractional converter.

A 3-wire control interface with five registers for writing and one for reading is similar to the previously considered one, which has a channel for dividing the reference frequency from the REF input. But at the same time, the MAX2880 does not have a built-in VCO unit, but an external VCO controlled from the CP output is used. You can put the MAX2880 in low power mode by setting SHDN = 1 (register 3, bit 5) or, as with other MAX synthesizers, low on the CE pin.

The frequency of the MAX2880 phase detector is determined by the following formula:

Here fREF is the input reference frequency. DBR (register 2, bit 20) sets the input frequency doubling mode fREF. RDIV2 (register 2, bit 21) sets the fREF division mode to 2. R (register 2, bits 19 ... 15) is the value of the 5-bit programmable reference divider (1 ... 31). The maximum fPFD is 105 MHz for Fractional-N and 140 MHz for Integer-N. The R divisor is cleared when RST (register 3, bit 3) = 1.

The frequency of the external VCO is determined by the formula:

Where N is the value of the 16-bit divisor N (16 ... 65535) programmed through bits 30 ... 27 (MSB) of register 1 and bits 26 ... 15 of register 0 (LSB). M - fractional coefficient value (2 ... 4095), programmed through bits 14 ... 3 of register 2. F - fractional division value, programmed through bits 14 ... 3 of register 0. In Fractional-N mode, the minimum value of N is 19, and the maximum is 4091 The N divisor is cleared when RST = 1 (register 3, bit 3). PRE - Input prescaler control, where 0 means division by 1 and 1 means division by 2 (register 1, bit 25). If the input frequency is higher than 6.2 GHz, then PRE = 1.

RF inputs

Differential RF inputs (Table 3) are connected to high impedance input buffers that control the demultiplexer to select one of two frequency ranges 0.25 ... 6.2 GHz or 6.2 ... 12.4 GHz. To operate in the upper range, a prescaler by 2 is used, selected by setting the PRE bit = 1. When operating in a single-channel version, the unused RF input is connected to the common output through a 100 pF capacitor.

A possible variant of the MAX2880 switching circuit is shown in Figure 5.

Table 3. Assignment of MAX2880 pins

Output	Name	Function
1	GND_CP	General conclusion for the charge pump generator. Connects to the common bus of the main board
2	GND_SD	General conclusion for the sigma-delta modulator. Connects to the common bus of the main board
3	GND_PLL	General conclusion of the PLL. Connects to the common bus of the main board
4	RFINP	RF positive input for prescaler. If not used, it is connected through a capacitor to the common terminal
5	RFINN	Negative RF input for prescaler. Connects to the output of the VCO via a capacitor
6	VCC_PPL	PLL power supply
7	VCC_REF	REF channel power supply
8	REF	Frequency reference input
9,1	GND	Connects to the common terminal of the power supply on the board
11	CE	Chip selection. A low logic level on this pin turns off the power of the device.
12	CLK	Serial sync input
13	DATA	Serial data input
14	LE	Load Enable Input
15	MUX	Multiplexed data input / output
16	VCC_RF	Power supply for RF output and dividers
17	VCC_SD	Power supply for sigma-delta modulator
18	VCP	Charge pump power supply
19	RSET	Charge pump input current range input
20	CP	Charge pump output. Connects to external filter input
–	EP	Heat sink area. Connects to the bus of the common power wire of the main board

Development Tools: Demo Boards and Software

Maxim Integrated hardware and software tools can significantly simplify the development process and shorten the implementation time for new solutions.

MAX2870 / MAX2871 Evaluation Kit Boards

Demo Boards MAX2870 / MAX2871(Figure 6) simplifies testing and evaluating the MAX2870 and MAX2871 synthesizers. Each board is equipped with standard SMA connectors for input signal sources, 50 ohm terminations, signal or spectrum analyzers. There is a USB connector for connection to a computer with preinstalled special software.

The sequence of actions when working with evaluation boards is as follows.

• download software from www.maximintegrated.com/evkitsoftware;
• unpack and install this software (Figure 7);
• after launching the MAX287x.exe file, select the type of microcircuit (MAX2870 or MAX2871) and press the “Continue” button. A working graphical interface will appear on the screen;
• check the USB cable connection by the green rectangle in the lower right corner of the work screen;
• make sure the TCXO frequency (U2) of the board matches the REF.FREQ of the software. If not, enter the required value in MHz (50 by default) and press “Enter”;
• press the “Defaults” buttons and then “Send All” located at the top of the work screen;
• enter the required value of the output frequency in MHz in the RF_OUTA or RF_OUTB window and press “Enter”;
• make sure the PLL Lock indicator in the lower left corner is green.

Use a signal analyzer to evaluate the performance of the MAX2870 or MAX2871. The default is an external 50 MHz frequency reference. However, you can use other values ​​after changing the values ​​in the programmable registers accordingly.

Output signal level

They use 3dB attenuators to load balance the unused outputs. Thus, the measured power at the outputs of the evaluation board (SMA connectors) becomes 3 dB below the real level. To measure the true output level, remove the attenuators and connect all active, unused outputs to 50 ohms.

Export / import of register settings

To export register settings from the MAX2870 / MAX2871, follow these steps:

• select with the mouse the inscription “Reg → Clip” in the lower left corner of the working screen, after which the values ​​of the registers will be saved in the clipboard;
• paste the contents of the clipboard into any test editor.
• To import settings for the MAX2870 / MAX2871 registers, follow these steps:
• copy register settings (comma separated) from a text editor to the clipboard;
• select with the mouse the inscription “Clip → Reg” in the lower left corner of the working screen;
• click the “Send All” button in the upper right corner of the home screen.

MAX2880 Evaluation Kit Board

The evaluation board for the MAX2880 includes a direct wideband PLL frequency synthesizer as well as an external 5840 ... 6040 MHz VCO, a 50 MHz temperature compensated crystal oscillator (TCXO), a passive feedback filter, and low dropout regulators.

The software runs on computers running Windows starting from XP version.

In addition, the MAX2880 Evaluation Kit requires a Maxim INTF-3000-to-USB interface board, a 20-wire ribbon cable for communication between the interface and evaluation boards. To connect the evaluation board to a computer, a USB Type A to Type B cable is required. The evaluation board also requires an external 6V / 150mA power supply.

The connection diagram is shown in Figure 8, and the boards themselves are shown in Figure 9.

The software for operation is downloaded from www.maximintegrated.com. Installation and operation is the same as described for the MAX2870 / MAX2871 Evaluation Kit. The working screen of the program is shown in Figure 10.

Conclusion

Maxim Integrated's MAX2870, MAX2871, and MAX2880 frequency synthesizers offer extended RF performance and can be used in high-fidelity microwave sources in a wide variety of telecommunications, navigation and instrumentation applications.

Demo boards and specialized software offered by the company can speed up the process of development, customization and implementation of samples of new technology.

Literature

1. https://datasheets.maximintegrated.com/en/ds/MAX2870.pdf.
2. https://datasheets.maximintegrated.com/en/ds/MAX2871.pdf.
3. https://datasheets.maximintegrated.com/en/ds/MAX2880.pdf.
4. https://datasheets.maximintegrated.com/en/ds/MAX2870EVKIT.pdf.
5. https://datasheets.maximintegrated.com/en/ds/MAX2880EVKIT.pdf.

and - low noise differential op amps

MAX44205 and MAX44206 production of the company Maxim integrated Are low noise fully differential operational amplifiers designed to operate with precision high speed 16/18/20 bit A / D converters such as.
A unique combination of characteristics, a wide range of supply voltages (2.7 ... 13.2 V), low power consumption and wide bandwidth allow their use in high-performance low-power data acquisition systems.
Both amplifiers, through the VCOM pin, allow you to control the common-mode output voltage, which in some cases greatly simplifies the circuitry of the measuring channel and normalizes the DC component of the output signal in accordance with the requirements of the ADC.
The MAX44205 features an optional output voltage limiting feature that limits the output voltage to within the ADC full scale when the amplifier's supply voltage is higher than the converter's maximum input voltage.
In low power mode, the amplifiers draw only 6.8 μA of current, which increases battery life in stand-alone measurement systems or reduces overall system power consumption between measurements.
The amplifiers are available in miniature yet easy-solder 12-pin µMAX® and 10-pin TDFN packages. Operating temperature range -40 ... 125 ° C.
To evaluate the parameters of the amplifiers, a demo board has been developed. MAX44205EVKIT #... Also the MAX44205 is used as an ADC driver on the demo board. MAX11905DIFEVKIT #.
Recommended Amplifier Applications:

• active filters;
• high-speed process control systems;
• Medical equipment;
• conversion of common-mode signals to differential;
• differential signal processing.

Babkovsky A.P., Seleznev N.E. Yu. E. Sedakova GSP-486, N. Novgorod - 603950, Russia tel .: 8312-666202, ext. 295, e-mail: [email protected]

Abstract - The results of work on the design of a simple C-band microwave synthesizer based on a single-chip phase automatic frequency control chip are presented.

I. Introduction

An increase in operating frequencies to the millimeter wavelength range in short-range radar devices with Doppler processing of reflected signals requires a significant increase in the stability of the radiated oscillations.

The use of signal processing circuits based on measuring the Doppler shift at intermediate frequencies in the decimeter frequency range to maximize the efficiency of the device requires the use of coherent generators in the path of the transmitter and receiver.

Currently, the most optimal way to obtain coherent signals for such millimeter-wave systems is to use frequency synthesizers in the centimeter-frequency range and then multiply and amplify them.

As a rule, such synthesizers are built according to multi-loop circuits using mixers, dividers and frequency multipliers.

However, in last years the upper operating frequency of single-chip synthesizers with a phase locked loop (PLL) has risen to the middle of the C-band.

Currently, Skyworks and Analog Devices are the leaders in the production of single-chip PLL synthesizers for this frequency range.

In the Russian market of electronic components, the products of Skyworks Inc. represented by the company: LLC "Radiocomp", Moscow.

Since 1993, after signing a direct license agreement with Analog Devices, ZAO Argussoft Company, Moscow, has been regularly updating and offering developers a full range of components and debugging devices.

The company "MEI Electronic Components", Moscow provides developers with detailed materials on the use of PLL microcircuits synthesizers from different manufacturers.

Raising the upper operating frequency of PLL synthesizers to C-band frequencies made it possible to create single-loop synthesizers, rather simple in structure.

In a number of cases, such an approach to the construction of a master oscillator (MO) and local oscillators is more advantageous from the point of view of technical, mass-dimensional and economic indicators.

The main parameters of some PLL synthesizer microcircuits operating in the C-band are shown in Table 1.

Tab. 1. Comparative characteristics of PLL synthesizer microcircuits.

Table 1. Comparison characteristics of PLL synthesizers' ICs

II. Main part

A functional diagram of a ZG and a local oscillator of this type based on a one-loop frequency synthesizer is shown in Figure 1.

Fig. 1. Synthesizer block diagram.

Fig. 1 Synthesizer block diagram

where Ref. Gen. - precision low-noise reference crystal oscillator GK62-TS, pS - microcontroller, PLL IC - synthesizer microcircuit, LPF - low-pass filter, Scaling amplifier - scaling operational amplifier, Dielectric Resonator VCO - voltage controlled oscillator (VCO) based on a dielectric resonator, Isolator - Microwave valve, Directional Coupler - directional coupler.

Taking into account our own experience in the development of microwave synthesizers and the results of studying various PLL synthesizer microcircuits, the CX72302 microcircuit with a fractional variable division ratio of Skyworks Inc. was selected for the development of the MO and the local oscillator. ...

Main characteristics of the СХ72302 microcircuit:

■ maximum output frequency of the main channel - 6.1 GHz;

■ auxiliary - 1000 MHz;

■ limiting working ICPD - 25 MHz;

■ guaranteed frequency switching time no more than 100 µs;

■ self-noise level -128 dB / Hz;

■ frequency step less than 400 Hz.

The use of СХ72302 allows for sufficient

high operating frequency of a pulsed frequency-phase detector (PFD) F = 16.384 MHz to obtain a frequency tuning step of 250 Hz due to a high degree of granularity (262144). An increase in the operating frequency of the ICPD leads to a decrease in the frequency multiplication factor of the PLL loop and an improvement in the noise parameters of the signal.

To reduce the noise level in the output signal, a generator with a high-Q dielectric resonator (DR) is used. Linear frequency tuning in such a generator is carried out using a ZA627A-6 varicap weakly coupled to the DR. The use of the 2T963A-2 transistor makes it possible to obtain an output power of the generator of the order of 50 mW.

The microwave signal from the VCO output is fed through a gate and a directional coupler to the output of the frequency synthesizer (the output power is + 15dBm - about 30 mW). Some of the power from the directional coupler (25 dB crossover attenuation) is diverted to the input of the PLL.

The parameters of the low-pass filter in the feedback loop of the PLL were calculated according to the method of the National Semiconductor company. In the Math-CAD2000 program, the operation of the PLL loop was simulated and its stability in the operating frequency range was checked.

At the output frequencies of the synthesizer in the middle of the C-band, the frequency multiplication factor of the PLL loop reaches 380 (the operating frequency of the phase detector is 16 MHz). Spectral density of phase noise of the reference crystal oscillator GK-62TS-

0 is minus (145 - 155) dB / Hz. The spectral density of the phase noise of the PLL microcircuit is 128 dB / Hz. Therefore, the spectral density of the phase noise of the generated signal is determined by the microcircuit and is

UV = -128+ 20 log 380 = -77 dB / Hz.

The synthesizer's output frequency is controlled by an Atmel AT90S8515-8PI microcontroller. To speed up the transient process, the switching of frequencies is performed at the maximum current of the phase detector. After capturing a given frequency, the phase detector current decreases to the nominal level, which leads to a decrease in the level of the discrete component with the phase detector comparison frequency in the synthesizer output signal spectrum. After switching the synthesizer, the microcontroller goes into "sleep" mode with its crystal oscillator turned off to reduce noise from the digital part of the circuit.

Structurally, the synthesizer is made in the form of a set of separate units interconnected by rigid coaxial cables. For the PLL microcircuit and the accompanying strapping, a printed circuit board made of FR-4 fiberglass with a thickness of 0.8 mm was used. Despite the relatively high operating frequency, the use of a substrate made of an inexpensive material is quite justified.

III. Experiment

Experimental studies of the noise parameters of the frequency synthesizer were carried out using the device for determining the spectral density of phase noise НР3048А.

The spectral density of the phase noise of the considered simple one-loop frequency synthesizer at large offsets from the carrier is:

10 kHz -92 dB / Hz;

100 kHz -117 dB / Hz.

Due to the weak connection of the varicap with the dielectric resonator, it was possible to obtain quite good noise parameters of the synthesizer, but its tuning band does not exceed 50 MHz when the control voltage on the varicap is changed from 1 to 25 V.

To expand the operating frequency range of the synthesizer, you can use a controlled generator based on YIG. But this will require changing the frequency control circuit.

IV. Conclusion

The use of a single-chip microcircuit with a fractional division factor in the feedback loop of the PLL allows the design of compact frequency synthesizers according to a single-loop circuit with output frequencies up to the upper operating frequency of the PLL microcircuit with a frequency tuning step in such a single-loop system of less than 400 Hz and an acceptable level of spectral density of phase noise ...

V. References

HF and SHF Radio components of foreign manufacturers. Price list. Issue 5.M. 2004.

Www.argussoft.ru

"MEI Electronic Components" Summer'2004.

RF / microwave components, electromechanics, power devices. Electronic catalog 2004

Babkovsky A.P. Experience in designing PLL synthesizers based on microcircuits from QUALCOMM and Mini-Circuits for a unit of reference signals of a millimeter-wave level gauge. - In the book. "8th International Crimean Conference" Microwave Engineering and Communication Technologies ". Conference proceedings ”[Sevastopol, 14-17 Sept. 1998]. Sevastopol: Weber, 1998, vol. 2, p. 667-668.

Babkovsky A. P., Seleznev N. E. Hybrid PLL / DDS frequency synthesizers. - In the book. "11th International Crimean Conference" Microwave Engineering and Communication Technologies ". Conference proceedings ”[Sevastopol, 10-14 Sept. 2001]. Sevastopol: Weber, 2001, pp. 112-114.

A. P. Babkovsky, N. Ye. Seleznev. Fast octave microwave synthesizer with a small frequency tuning step. - In the book. "13th International Crimean Conference" Microwave Engineering and Communication Technologies ". Conference materials ”[Sevastopol, 8-12 Sept. 2003]. Sevastopol: Weber, 2003, pp. 136-138.

Www.skyworksinc.com

SINGLE-LOOP SYNTHESIZER FOR C-BAND WITH ULTRA FINE FREQUENCY STEP

Babkovsky A., Seleznev N.

Federal State Owned Unitary Enterprise Measuring Systems Research Institute names after Yu. Ye. Sedakov GSP-486, Nizhny Novgorod - 603950, Russia e-mail: [email protected]

Abstract - Considered in this paper are results of C-band simple frequency synthesizer design on the basis of single loop PLL.

Rising of operating frequencies of a short range Doppler radar up to MM-band demands a great improvement of transmitted signal stability.

The principle of signal processing is based on the reflected signals Doppler frequency measurement at the intermediate frequency (in UHF range). Thus, the transmitter chain exciter and the receiver local oscillator (LO) must be coherent.

At present the most preferred approach in coherent signals generation is the use the C-band frequency synthesizers along with multipliers and amplifiers.

Frequently those synthesizers are designed using multiloop schematic in conjunction with frequency mixers, dividers and multipliers.

During the last years the PLL IC's upper operating frequency was increased up to C-band. Now the leader manufacturers of the PLL IC's for this frequency band are Skyworks and Analog Devices. Increase of IC operating frequency allows to design simple C-band single-loop frequency synthesizers.

In some cases this approach may is more preferable.

The block diagram of the transmitter exciter on the basis of single-loop PLL is shown in Fig. 1. Taking into account our skills in synthesizer design, Skyworks CX72302 Fractional-N PLL IC was chosen for the exciter and LO design. For more details visit www.skyworksinc.com website.

Using CX72302 we can get 250Hz frequency step only with phase detector comparison frequency value 16.384MHz due to the high grade fractionality, 2 18. High phase detector frequency leads to decrease of the main divider value N and noise parameters improvement.

High-Q dielectric resonator oscillator (DRO) is used for obtaining better noise performance out of PLL passband. Linear frequency sweep is carried out using a varicap having weak coupling with DR. The output power of DRO generator is 50 mW.

The signal passes through the isolator and directional coupler to the synthesizer output (output power is + 15dBm - approx. 30 mW). A part of the power from the coupled port of the directional coupler is directed to the PLL IC input.

The loop filter components were calculated by the methods proposed by National Semiconductor. Loop stability analysis was evaluated in MathCAD 2000.

The main loop division ratio is increased up to 380 (phase detector frequency 16 MHz) at the frequencies about 6GHz. Phase noise spectral density of the PLL IC is -128 dB / Hz. Thus the phase noise spectral density in the PLL passband is determined by PLL IC noise, although the phase noise of the reference generator is (-145 ... -155 dB / Hz) and equal to -77dB / Hz.

Control of the synthesizer output frequency is carried out by Atmel AT90S8515-8PI microcontroller. In order to minimize the frequency switching time, the charge pump current is increased to its maximum value. After locking the charge pump current is switched to the nominal value and microcontroller is switched over to the sleep mode along with clock generator turning off. This allows to suppress noise in the output spectrum of the digital circuitry.

Noise parameters of the synthesizer output signal were measured by HP3048A test set.

Phase noise floor of the tested single-loop PLL synthesizer within offsets from the carrier is:

Frequency offset Phase noise floor

10 kHz -92 dB / Hz

100 kHz -117 dB / Hz

The weak coupling between the varicap and dielectric resonator in the tuned generator provides noise parameters rather good but the synthesized frequency band is too narrow (approximately 50 MHz within varicap tuning range from 1 to 25 volts).

It is possible to use YIG tuned oscillator to extend the synthesized frequency band. But in this case the frequency tuning circuitry must be changed.

Single chip Fractional-N PLL allows to construct small size single-loop frequency synthesizers for the frequencies up to the maximum operating PLL IC frequency with the frequency step less than 400 Hz and acceptable phase noise level.

Holders of the patent RU 2580068:

The invention relates to radio engineering and can be used in transmitting and receiving devices of the microwave frequency range. The technical result is to increase the stable operation when tuning the frequency of the input microwave signal. The microwave frequency synthesizer contains a voltage controlled microwave generator (VCO), a directional coupler, a microwave mixer, a source of an input microwave signal, a first frequency divider with a variable division factor, a frequency-phase detector, a second frequency divider with a variable division factor, a reference signal source, a filter low frequencies, a phase comparator, a waiting multivibrator, two diodes and an operational amplifier. 4 ill.

The invention relates to radio engineering, namely to wide-range microwave frequency synthesizers with preliminary, initial, setting of the frequency of the microwave voltage-controlled generator (VCO) included in the wide-range phase-locked loop (PLL) of the microwave frequency synthesizer and can be used in transceiving devices of the microwave frequency range ...

Known systems for active frequency synthesis, in which the filtering of oscillations of the synthesized frequencies is carried out using an active filter in the form of a phase-locked loop. In this case, the signal frequency is converted, for example, by dividing into the low-frequency range, where it is compared with the frequency of the reference generator and the voltage of the self-tuning of the voltage-controlled microwave generator (VCO) is generated. Active synthesis systems provide higher rejection of spurious spectral components and carrier phase noise. However, in this scheme, due to the high frequency division ratio of the VCO, it is impossible to achieve a low noise level of the synthesizer output signal.

Known microwave frequency synthesizer, which implements the principle of active synthesis with a PLL loop, which is selected as a prototype of the present invention. The microwave frequency synthesizer contains a microwave VCO, the output of which is connected through a directional coupler to the output of the microwave frequency synthesizer and to the first input of the microwave mixer, the second input of which is connected to the output of the source of the input microwave signal with a frequency f input of the microwave, the output of the microwave mixer is connected to the input of the first frequency divider (DF) with a variable division factor n, the output of which is connected to the first input of the frequency-phase detector (PFD), the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division factor m, the input of which is connected to the source of the reference signal of frequency f OP, and the output of the frequency-phase detector through a low-pass filter (LPF) is connected to the input of the microwave VCO. In this case, the directional coupler, mixer, first frequency divider, PFD and LPF form a PLL loop.

The known microwave frequency synthesizer makes it possible to achieve a low level of phase noise of the output signal of the microwave frequency synthesizer with a frequency f MF by reducing the division ratio of the first frequency divider when used as an input microwave signal with a frequency f input of a microwave signal with a low level of phase noise. In addition, decreasing the division ratio of the first frequency divider allows you to increase the gain of the PLL loop. Since in such a scheme the frequency of the input microwave signal f in the microwave is selected from the condition f in microwave> f midrange, to maintain a constant value of the gain of the PLL loop of the microwave frequency synthesizer, it is necessary to compensate for the change in the division factor of the first frequency divider by changing the slope of the frequency tuning of the microwave VCO in order to maintain PLL loop control bands.

However, if the drifts of the frequency f VCO of the UHF VCO are more than 2 f IF (where the intermediate frequency f IF = f in the UHF -f VCO), then in this microwave frequency synthesizer there will be phase synchronization failures, which will lead to the loss of the synthesizer's performance.

In addition, the known microwave frequency synthesizer works only if the input microwave signal with a fixed frequency f input of the microwave is fed to the second input of the microwave mixer. When the input microwave signal is fed to this input of the microwave mixer with a variable (tunable) microwave frequency f input in a band greater than or equal to 2 f IF, phase synchronization disturbances can also occur in the microwave frequency synthesizer.

The technical problem of the present invention is to create a wide-range microwave frequency synthesizer with a low level of phase noise and a short frequency tuning time of the output signal f MF synthesizer, ensuring the absence of phase synchronization violations when changing (tuning) the frequency of the input microwave signal f input microwave in a band equal to or greater than the doubled frequency of the intermediate frequency signal f IF, where f IF = f in the microwave -f VCO, as well as ensuring the preservation of phase synchronization when the frequency f VCO of the microwave signal of the VCO is more than 2 f IF.

The technical result is to prevent phase synchronization violations caused by transient processes in the PLL loop, and to ensure stable operation of the microwave frequency synthesizer during operation, including when tuning the frequency f input of the microwave input microwave signal

The essence of the technical solution lies in the fact that the proposed microwave frequency synthesizer contains a voltage controlled microwave generator (VCO), the output of which is connected to the input of a directional coupler, the first output of which is the output of the microwave frequency synthesizer, and the second output of the directional coupler is connected to the first input of the microwave mixer , the second input of the microwave mixer is connected to the output of the input microwave signal source, the output of the microwave mixer is connected to the input of the first frequency divider with a variable division ratio, the output of which is connected to the first input of the frequency-phase detector, the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division ratio, the input of which is connected to the output of the reference signal source, and a low-pass filter is included between the frequency-phase detector and the microwave VCO. The microwave frequency synthesizer additionally contains a phase comparator, a waiting multivibrator, two diodes and an operational amplifier. In this case, the first and second outputs of the frequency-phase detector are connected, respectively, to the first and second inputs of the operational amplifier, the output of which is connected to the input of the microwave VCO, and the low-pass filter is connected between the first input of the operational amplifier and its output, the first input of the phase comparator is connected to the output of the first a frequency divider with a variable division ratio and the first input of a frequency-phase detector, the second input of a phase comparator is connected to the output of a second frequency divider with a variable division ratio and to a second input of a frequency-phase detector, the output of a phase comparator is connected to an input of a waiting multivibrator, the first output of a waiting multivibrator connected through the first diode with the first output of the frequency-phase detector and with the first input of the operational amplifier, the second output of the waiting multivibrator is connected through the second diode with the second output of the frequency-phase detector and with the second input of the operational amplifier. Moreover, the first and second diodes are turned on opposite to each other, while the microwave VCO, directional coupler, microwave mixer, first frequency divider, frequency-phase detector, operational amplifier and low-pass filter form a phase-locked loop (PLL) under the condition: τ m> τ PLL, where T M is the oscillation period of the waiting multivibrator, τ PLL is the time to establish synchronization in the phase-locked loop.

The inclusion of a phase comparator and a waiting multivibrator with two oppositely connected diodes at the output into the circuit of the microwave synthesizer makes it possible to preset the frequency f VCO of the microwave VCO signal when the phase synchronization in the PLL loop is disturbed, which occurs when switching the frequency f input of the microwave input microwave signal or during drifts frequency f VCO of the microwave VCO signal, for example, when the microwave synthesizer is turned on, which ensures fast recovery of phase synchronization and increases the stability of the microwave frequency synthesizer. In this case, after the restoration of the PLL loop, the waiting multivibrator is turned off and does not affect the further operation of the PLL loop.

An operational amplifier with a low-pass filter in the feedback loop forms the control bandwidth of the PLL loop.

The time between the end of the first pulse and the beginning of the next pulse of the waiting multivibrator, determined by the RC circuit of this multivibrator, must be greater than the time it takes to establish synchronization in the PLL loop, that is, the condition must be met:

T M -τ m> τ PLL.

The invention is illustrated by drawings.

FIG. 1 shows a block diagram of the proposed microwave frequency synthesizer, where

1 - microwave generator (VCO) with frequency f VCO (control voltage U UPR);

3 - microwave mixer;

4 - source of input microwave signal with frequency f input microwave;

5 - the first frequency divider with a variable division ratio n;

6 - frequency-phase detector (output voltage U PFD);

7 - second frequency divider with variable division factor m;

8 - a source of a reference signal with a frequency f OP;

9 - operational amplifier;

10 - low pass filter;

11 - phase comparator (output voltage U FC);

12 - waiting multivibrator (output voltage forward U m1 and inverse

13 - the first diode;

14 - the second diode;

f IF = f input microwave -f VCO - intermediate frequency signal;

f MF - output signal of the microwave frequency synthesizer.

FIG. 2 shows the timing diagrams of the input U FC and output U m1 and U m2 voltages of the waiting multivibrator, which is part of the proposed microwave frequency synthesizer, where

T M - oscillation period of the waiting multivibrator 12;

τ m - the duration of the pulse of the waiting multivibrator 12;

τ PLL is the time to establish synchronization in the phase-locked loop.

FIG. 3 shows the tuning band of the output microwave signal with a frequency f MF = f VCO relative to a fixed frequency f input of the microwave input microwave signal of the proposed microwave frequency synthesizer.

FIG. 4 shows the tuning band of the output microwave signal with a frequency f MF = f VCO relative to the tunable frequency f in the microwave input microwave signal of the proposed microwave frequency synthesizer.

The proposed microwave frequency synthesizer, the block diagram of which is shown in Fig. 1, contains a voltage controlled microwave generator (VCO) 1, the output of which is connected to the input of the directional coupler 2, one output of which is the output of the microwave frequency synthesizer, and the other output of the directional coupler 2 is connected to the first input of the microwave mixer 3, the second input of which is connected to the output source of input microwave signal 4 with frequency f input microwave. The output of the microwave mixer 3 is connected to the input of the first frequency divider 5 with a variable division factor n, the output of which is connected to the first input of the frequency-phase detector 6. The second input of the frequency-phase detector 6 is connected to the output of the second frequency divider 7 with a variable division factor m, the input which is connected to the output of the source of the reference signal 8 with a frequency f OP. Two outputs of the frequency-phase detector 6 are connected to two inputs of the operational amplifier 9, the output of which is connected to the input of the microwave generator VCO 1, while a low-pass filter 10 is connected between the first input of the operational amplifier 9 and its output 10. The first input of a phase comparator added to the circuit 11 is connected to the output of the first frequency divider 5 and the first input of the frequency-phase detector 6, the second input of the phase comparator 11 is connected to the output of the second frequency divider 7 and the second input of the frequency-phase detector 6. The output of the phase comparator 11 is connected to the input of the waiting multivibrator 12, direct the output of which through the first diode 13 is connected to the first output of the frequency-phase detector bis by the first input of the operational amplifier 9, the inverse output of the waiting multivibrator 12 through the second diode 14 is connected to the second output of the frequency-phase detector 6 and to the second input of the operational amplifier 9, the first and the second diodes are switched on opposite to each other. In this scheme, the microwave VCO 1, the directional coupler 2, the microwave mixer 3, the first frequency divider 5, the frequency-phase detector 6, the second frequency divider 7, the operational amplifier 9 and the low-pass filter 10 form a PLL loop.

The proposed microwave frequency synthesizer operates as follows. The output signal of the microwave VCO 1 with a frequency f VCO through the coupler 2 and the output microwave signal of the source of the input microwave signal 4 with a frequency f input of the microwave are fed to the microwave mixer 3, at the output of which the intermediate frequency signal f IF is extracted, which is fed to the input of the first frequency divider 5 and after dividing by a factor n, the signal from the output of the first frequency divider 5 is fed to the first input of the frequency-phase detector 6. The signal of the reference frequency f OP from the output of the reference signal source 8 is fed to the input of the second frequency divider 7, where the frequency is divided by the factor m. The signal from the output of the second frequency divider 7 is fed to the second input of the frequency-phase detector (PFD) 6, in which it is compared with the signal received from the output of the first frequency divider 5, and a control voltage U PFD is generated at the two outputs of the frequency-phase detector 6, the value and sign of which are proportional to the difference in frequencies and phases of the compared signals. This control voltage U PFD through the operational amplifier 9 and the low-pass filter 10, included in the feedback circuit of the operational amplifier 9, is fed to the control input of the microwave VCO 1 as a control voltage U UPR. synchronization in the PLL loop.

The conditions for performing frequency-phase synchronization in the PLL loop are the equality of the frequencies and phases of the signals supplied to the inputs of the frequency-phase detector, that is, f OP / m = f IF / n, φ OP = φ IF,

where f IF = f input microwave -f VCO,

m is the division factor of the frequency of the reference signal with the frequency f OP;

n is the frequency division factor of the signal of the intermediate frequency f IF;

φ OP - phase of the reference signal with frequency f OP;

φ IF - phase of the intermediate frequency signal f IF.

When tuning the frequency of the input microwave signal f input microwave in a band equal to or greater than the doubled frequency of the intermediate frequency signal f IF, where f IF = f input microwave -f VCO, as well as when the frequency of the microwave signal VCO f VCO is more than 2 f IF, the input microwave signal f in the microwave in the present invention passes through the PLL loop of the microwave frequency synthesizer, that is, through the phase comparator 11, the waiting multivibrator 12, as well as the oppositely connected diodes 13, 14.

In the presence of phase synchronization in the PLL loop, a control signal is sent from the output of the phase comparator 11 to the waiting multivibrator 12, which turns off the waiting multivibrator 12, that is, the output voltage of the phase comparator 11 U FC (for example, the level of the transistor-transistor logic TTL) in the form of a logical unit. At this time, the waiting multivibrator 12 does not generate pulse output signals at the direct and inverse outputs with voltages U M1, U M2, respectively, and does not affect the operation of the PLL loop. At the direct and inverse outputs of the waiting multivibrator 12, constant voltages U M1 and U M2 are set in antiphase, corresponding to a logical zero and a logical one). Timing diagrams of the input U FC and output U M1 and U M2 voltages of the waiting multivibrator 12 are shown in FIG. 2

If the synchronization of frequency and phase in the PLL loop is violated, the signal U FC in the form of a logical zero from the output of the phase comparator 11 starts the waiting multivibrator 12, which at the direct and inverse outputs generates output pulse signals with voltages U M1 (corresponding to a logical unit) and U M2 (corresponding logical zero), coming through diodes 13, 14, respectively, to the first and second inputs of the operational amplifier 9. During the action of the pulse of the waiting multivibrator 12, that is, during the duration τ m of the pulse of the waiting multivibrator 12, depending on the phasing of the inputs of the PFD 6, at the output operational amplifier 9 is set to the maximum or minimum value of the voltage control of the frequency of the microwave signal VCO 1. In this case, the conditions for frequency-phase synchronization are violated (f OP / m = f IF / n, φ OP = φ IF) and the frequency-phase detector 6 generates voltage U PFD, which ensures the restoration of synchronization (that is, the start of the synchronization process i) in the PLL loop. When restoring the frequency-phase synchronization in the PLL loop, the phase comparator 11 turns off the waiting multivibrator 12 (at its outputs, constant voltages are again set in antiphase, corresponding to a logical zero and a logical one). In the event of a repeated violation of the frequency-phase synchronization in the PLL loop or in the event of a failure in the operation of the PLL loop, the phase comparator 11 again starts the waiting multivibrator 12 and the entire synchronization recovery process is repeated.

In some cases, for the PLL loop to work, excluding the violation of the frequency-phase synchronization in it, it is necessary that the transient process of tuning the microwave VCO frequency in the PLL loop starts from the lower (f VCO min) or upper (f VCO max) edge of the microwave VCO operating range to the frequency lock point at which f VCO = f MF, that is, the initial voltage level supplied to the control input of the microwave VCO 1 (in the transient mode preceding the frequency lock), was always equal to the minimum or maximum value... This is determined by the position of the frequency f VCO of the output microwave VCO signal relative to the frequency f in of the microwave input microwave signal. In this case, two main modes of operation of the microwave frequency synthesizer are possible, in which the synchronization in the PLL loop is possible.

Consider the first mode of operation of the microwave frequency synthesizer shown in FIG. 3. Suppose that the frequency f input of the microwave input microwave signal is fixed and exceeds f MF (as in the prototype), and the tuning band of the microwave VCO 1 (Δf VCO) is large enough, for example, significantly exceeds the value of 2 f IF. In this case, during the transient process preceding the capture of the frequency, the frequency-phase detector 6 can receive a mirror frequency signal from the output of the microwave mixer 3 (at the point of synchronization breakdown, in which f VCO = f 1 MF, where f 1 MF = f in microwave + f IF), which will lead to a breakdown of synchronization in the PLL loop, the transition of the frequency signal f VCO microwave VCO to the uppermost position corresponding to the frequency f VCO max and, as a consequence, to failure of the microwave frequency synthesizer. The circuit of the microwave frequency synthesizer selected as a prototype does not provide for the possibility of getting out of this situation. In the proposed microwave frequency synthesizer, this problem is solved as follows.

The phase comparator 11 in the frequency-phase synchronization mode (f OP / m = f IF / n, φ OP = φ IF) generates at its output a signal U FC corresponding to a logical unit (log. "1"). This output of the phase comparator 11 is connected to the input of the waiting multivibrator 12, which is triggered by a signal corresponding to a logical zero (logical "0"). With an input signal equal to the log. "0", the first 13 and second 14 diodes are closed and the waiting multivibrator 12 does not affect the operation of the PLL loop. In the event that the phase synchronization mode is violated, a signal corresponding to the log appears at the output of the phase comparator 11. "0". This can occur when the microwave frequency synthesizer is turned on or when the frequency f of the reference signal is tuned. The signal corresponding to the log. "0" from the output of the phase comparator 11 starts the waiting multivibrator 12 and at its direct and inverse outputs during the pulse duration τ m voltage levels appear, equal to log "1" and log. "0" (that is, inverse to the previous state), so the first 13 and second 14 diodes open and a differential voltage is supplied to the first and second inputs of the operational amplifier 9, which causes the appearance of the initial (minimum) control voltage at the output of the operational amplifier 9, which is applied respectively to frequency control input of the microwave VCO 1, this sets the value of the frequency of the microwave VCO f VCO = f VCO min. After the end of the pulse of the waiting multivibrator 12, there is a pause equal to T M -τ m, where T M is the pulse repetition period of the waiting multivibrator 12. During this pause, the PLL loop adjusts the frequency f VCO of the microwave VCO signal from the minimum value f VCO min to the frequency , at which the frequency-phase synchronization occurs (the frequency lock point in Fig. 3). When tuning the frequency f VCO of the microwave VCO signal to a value at which f VCO = f MF (where f MF = f in the microwave -f IF) and if the condition f VCO ≤f in the microwave (in accordance with the phasing of the PFD 6) is met, then frequency-phase synchronization mode, in which f OP / m = f IF / n. At the output of the phase comparator 11 there is a signal corresponding to the log level. "1", which translates the multivibrator 12 into a standby state. If, for some reason, the synchronization process has not occurred, then the described cycle of establishing synchronization in the PLL loop is repeated. A necessary condition for locking the frequency, in this case, is that the pulse repetition period of the waiting multivibrator 12 must correspond to the condition: T M -τm> τ of the PLL loop, where

T M - pulse repetition period of the waiting multivibrator,

τ m - the duration of the pulse of the waiting multivibrator,

τ of the PLL loop - the time to establish synchronization in the PLL loop.

Consider the second mode of operation of the microwave frequency synthesizer shown in FIG. 4.

Suppose that at the initial moment in the microwave frequency synthesizer the condition of frequency-phase synchronization is fulfilled, while f in microwave = f in microwave1. In this case, the frequency of the output signal of the microwave frequency synthesizer f MF = f MF · 1 = f in MW1 -f IF. Then the frequency f in the microwave input microwave signal is quickly tuned in the band Δf in the microwave input microwave signal (as shown in Fig. 4) from the value f in the microwave1 to the value f in the microwave2 (in this case, the frequency tuning band of the input microwave signal Δf in the microwave is more than 2 f IF, where f IF = f in the microwave -f VCO. Simultaneously with the restructuring of the frequency f in the microwave, the frequency f VCO of the microwave VCO is re-tuned from the value f MF1 to the value f MF2. However, due to the inertia of the PLL loop, the The microwave signal (t AC microwave input) is always less than the time to establish synchronization in the PLL loop (τ PLL loop), that is, t AC microwave input ≤τ of the PLL loop.

As a result of the inertia of the PLL loop when tuning the microwave VCO frequency, conditions also arise for the violation of synchronization. For example, as shown in FIG. 4, when tuning the frequency f of the VCO from the initial value of f MF1 (in the upper part of the frequency tuning range of the microwave VCO) to the next lower value f MF2 in frequency. in the microwave mixer, a mirror intermediate frequency signal is generated at the point where f VCO = f 1 SCH2 = fin microwave2 + f IF. In this case (for a given phasing of PFD 6), the condition f VCO ≤f in microwave will not be met, that is, the frequency is not locked by the PLL loop, which causes a violation of the frequency-phase synchronization with "pulling" the frequency f VCO to the upper extreme value f VCO max frequency tuning range of the microwave VCO. To restore the frequency-phase synchronization in the PLL loop in the present invention, the synchronization cycle described in the first mode of operation of the microwave frequency synthesizer should be implemented. The microwave frequency synthesizer circuit, selected as a prototype, does not provide for the possibility of rapidly changing the frequency of the input microwave signal, and therefore, such a circuit does not allow for stable phase synchronization when the frequency of the input microwave signal is tuned.

The above-described modes of unstable operation of the PLL system in the known microwave frequency synthesizer, selected as a prototype of the invention, have been experimentally tested and confirmed.

On the basis of the proposed invention, samples of microwave frequency synthesizers have been developed and experimentally tested, which have confirmed stable operation with a fast recovery time of frequency-phase synchronization in various modes of operation of microwave frequency synthesizers - less than 100 μs.

Sources of information

1. Manasevich V. Frequency synthesizers. Theory and design. - M .: Communication, 1979

2. Ryzhkov A.V., Popov V.N. Frequency synthesizers in radio communication engineering. - M .: Radio and communication, 1991, p. 110-113.

Microwave frequency synthesizer containing a voltage controlled microwave generator (VCO), the output of which is connected to the input of a directional coupler, the first output of which is the output of the microwave frequency synthesizer, and the second output of the directional coupler is connected to the first input of the microwave mixer, the second input of the microwave mixer is connected to the output source of the input microwave signal, the output of the microwave mixer is connected to the input of the first frequency divider with a variable division ratio, the output of which is connected to the first input of the frequency-phase detector, the second input of the frequency-phase detector is connected to the output of the second frequency divider with a variable division factor, the input of which is connected with the output of the reference signal source, and a low-pass filter is connected between the frequency-phase detector and the microwave VCO, characterized in that the microwave frequency synthesizer additionally contains a phase comparator, a waiting multivibrator, two diodes and an operational amplifier, while the first and second outputs of the frequency-phase detector connected s respectively with the first and second inputs of the operational amplifier, the output of which is connected to the input of the microwave VCO, and the low-pass filter is connected between the first input of the operational amplifier and its output, the first input of the phase comparator is connected to the output of the first frequency divider with a variable division ratio and the first input of the frequency -phase detector, the second input of the phase comparator is connected to the output of the second frequency divider with a variable division ratio and to the second input of the frequency-phase detector, the output of the phase comparator is connected to the input of the waiting multivibrator, the first output of the waiting multivibrator is connected through the first diode to the first output of the frequency-phase detector and with the first input of the operational amplifier, the second output of the waiting multivibrator is connected through the second diode to the second output of the frequency-phase detector and to the second input of the operational amplifier, and the first and second diodes are connected opposite to each other, while the microwave VCO, directional coupler, microwave mixer, first frequency divider, frequency-phase detector, operational amplifier and low-pass filter form a phase-locked loop (PLL) under the condition: T M -τ m> τ PLL, where T M is the oscillation period of the waiting multivibrator, τ m is the duration pulse of the waiting multivibrator, τ PLL is the time of establishing synchronization in the phase-locked loop.

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When developing and setting up microwave devices, radio amateurs often have difficulties associated with the lack of measuring equipment for the required frequency range. The proposed frequency synthesizer can be made in an amateur environment. It operates in the 1900 ... 2275 MHz range. The frequency value is selected from several possible using a switch.

At relatively low frequencies (up to 100 ... 150 MHz), the problem of stabilizing the frequency of the generator is solved by using quartz resonators, at higher frequencies (400 MHz) - using resonators on surface acoustic waves (SAW resonators), at microwave frequencies dielectric resonators are used from high-quality ceramics and other high-quality resonators. Stabilization using passive components has its own advantages - simplicity and relatively low cost of implementation. Its main disadvantage is the impossibility of a significant change in the frequency of the generated signal without changing the frequency setting element.

The widely used integrated frequency synthesizers make it possible to implement fast electronic tuning of the generator (including microwave), while maintaining high frequency stability. Synthesizers are of direct and indirect types.

The advantages of direct synthesis are considered to be the high speed of frequency change and tuning with a small step. However, due to the presence in the synthesized signal of a large number of spectral components resulting from numerous nonlinear transformations, direct synthesis devices are rarely used in microwave equipment.

For microwave synthesis, synthesizers of the indirect type with a phase-locked loop (PLL) are often used. The principle of operation of the PLL, as well as the method for calculating the feedback filter, have been widely and repeatedly considered in the literature, for example, in. There are several freeware programs that allow you to calculate the optimal parameters for feedback filters, they can be found on the Internet at or .

Integrated synthesizers with PLL are of two types: programmable (frequency values ​​are set by external commands) and non-programmable (fixed multiplication and division factors of the reference frequency cannot be changed).

The disadvantages of non-programmable integrated synthesizers, for example, MC12179, include the need to use a quartz resonator with a precisely specified frequency, which is not always possible. Programmable synthesizers such as the UMA1020M do not have this drawback. In the presence of a control microcontroller, it is not technically difficult to tune such a synthesizer to a given frequency. The microwave oscillators with electronic frequency tuning, necessary for joint work with the synthesizer microcircuit, are available to the consumer in the form of functionally complete modules made using hybrid technology.

A diagram of a laboratory frequency synthesizer designed for checking and adjusting the tuning of equipment in the 2 GHz range is shown in Fig, 1. Its basis is the UMA-1020M (DA3) microcircuit, technical documentation for which can be found on the website of its manufacturer at .

The synthesizer also has a DA1 voltage controlled oscillator (VCO), a 10 MHz DA2 crystal oscillator and a DD1 microcontroller. The microwave signal from the VCO output is fed to the synthesizer output (connector XW1) and to the input of the main programmable frequency divider of the DA3 microcircuit. The signal of the exemplary frequency from the output of the DA2 generator is fed to an auxiliary programmable frequency divider, also included in the DA3 microcircuit.

The frequency division ratios by the main and auxiliary dividers are set by the DD1 microcontroller (Z86E0208PSC) by sending the appropriate commands over the three-wire data bus (pins 11-13 DA3). The source code of the control program is shown in table. 1. Internal memory the microcontroller is sufficient to store data on seven different frequencies. One of the frequency values ​​or the mode in which there is no signal at the output is selected with jumpers S1-S3 according to table. 2. The set mode takes effect at the moment the device is powered on, after which no manipulations with the switches affect its operation until it is switched on again. The HL1 LED should go out 1 s after the power is turned on. You can read about programming of Zilog microcontrollers in.

The synthesizer is assembled on a printed circuit board, appearance which is shown in Fig. 2. Applied resistors and capacitors for surface mounting.

Literature

1. Starikov O. PLL method and principles of synthesizing high-frequency signals. - Chip News, 2001, no. 6.
2. VCO Designer "s Handbook 2001. VCO / HB-01. - Mini-Circuits.
3. Glvdshtein M. A. Microcontrollers of the Z86 family from Zilog. Programmer's guide. - M .: DODEKA, 1999, 96 p.

In addition to the microwave synthesizer, the UMA1020M microcircuit contains one more, operating in the frequency range 20..300 MHz, 6n is not used in the described design.